(a) Field of the Invention
The present invention relates to a variable impedance circuit and, more particularly, to a variable impedance circuit having a plurality of impedance elements switched for connection between external terminals.
(b) Description of the Related Art
In an I/O circuit used for input/output of data in an LSI, the input impedance of the I/O circuit should be matched with the impedance of the transmission line transferring the data to/from the I/O circuit. Although the impedance matching scheme generally uses MOS transistors or resistors, there is a problem in that the resistances of the MOS transistors or resistors deviate from the design resistances due to characteristic variances associated therewith. Thus, a variable resistance circuit having an adjustment means for the impedance is used as the I/O circuit.
JP-A-2000-49583, for example, describes a variable resistance circuit, such as shown in FIG. 1, used for the impedance adjustment. The variable resistance circuit includes an impedance block 20 including a plurality of MOS transistors having different gate widths, a comparator 21 and a control unit 22.
The impedance block 20 has a basic structure wherein a plurality of MOS transistors are connected in parallel, and the gates of the MOS transistors are connected to outputs of AND gates, each of which has inputs connected to a signal line 15 and a corresponding control line 14. The signal line 15 is common to the AND gates, and the control lines 14 are connected to the control unit 22.
Each of the MOS transistors receiving the outputs of AND gates, which are connected to the control lines 14 assuming a high level, assumes ON- or OFF-state depending on the level of the signal line 15, thereby providing a signal current. On the other hand, the MOS transistors receiving the outputs of AND gates, which are connected to the control lines 14 assuming a low level, assumes an OFF-state.
The MOS transistor has a resistance in inverse proportion to the gate width (W) of the MOS transistor in a linear resistance region thereof, wherein the ON-current of the MOS transistor changes in proportion to the applied voltage. The ON-resistance rON of the MOS transistor is expressed by 1/gm, wherein the transconductance gm is in proportion to W/L, given L being the gate length of the MOS transistor. This fact allows the overall resistance of the MOS transistors to be changed by changing the total gate width of the MOS transistors which are ON.
In the configuration shown in FIG. 1, the MOS transistors have gate widths of 1W, 2W, 4W and 8W in accordance with powers of 2, the powers corresponding to the sequential order of the MOS transistors, i.e., xe2x80x9c0xe2x80x9d to xe2x80x9c3xe2x80x9d in this example. Thus, the overall resistance Z is expressed by the following formula:
Z=Z0/(S0xc3x971+S1xc3x972+S2xc3x974+S3xc3x978),
wherein Z0 represents a unit resistance corresponding to the unit gate width xe2x80x9cWxe2x80x9d, and Si (i=0, 1, 2, 3) represents xe2x80x9c1xe2x80x9d for the MOS transistor which is ON and xe2x80x9c0xe2x80x9d for the MOS transistor which is OFF. Thus, it is possible to select one of the specified overall resistances by controlling the levels of the control lines 14 at xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d. More specifically, Z can assume a resistance between Z0 and Z0/15.
In the conventional variable resistance circuit as described above, the overall resistance Z follows a hyperbola such as shown in FIG. 2, wherein the resistance Z obtained in the circuit is plotted against the code in decimal notation (code value), which defines the respective levels of the control lines 14. This fact may degrade the accuracy of the resistance obtained therein as will be detailed hereinafter.
For example, comparing the case where the resistance assumes the maximum (i.e., S0=1, and S1=S2=S3=0) and the case where the resistance assumes a value next to the maximum (i.e., S1=1 and S0=S2=S3, the step difference between the maximum and next to the maximum is as follows:
Z0xe2x88x92Z0/2=Z0/2xe2x80x83xe2x80x83(1).
On the other hand, comparing the case where the resistance assumes a minimum (i.e., S0=S1=S2=S3=1) and the case wherein the resistance assumes a value next to the minimum (i.e., S0=0, and S1=S2=S3=1), the step difference between the minimum and next to the minimum is as follows:
Z0/14xe2x88x92Z0/15=Z0/210xe2x80x83xe2x80x83(2).
It will be understood that the former step difference is extremely larger than the latter step difference.
Since the step difference is extremely larger in the region of a larger overall resistance in the conventional technique, as described above, the overall resistance actually obtained by controlling the levels of the control lines may fall outside the objective resistance range in the region of the larger overall resistance. In such a case, degradation of the signal wave may occur in the I/O circuit due to the mismatching of the impedance.
In view of the above problem in the conventional technique, it is an object of the present invention to provide a variable impedance circuit which is capable of achieving an overall impedance more likely to fall within an objective impedance range, with less variances in the resultant overall resistance.
The present invention provides, in a first aspect thereof, a variable impedance circuit including: a pair of external terminals; an impedance block including first through n-th impedance elements; and a control section for switching each of the impedance elements for connection between the pair of external terminals, thereby selecting one of overall impedances of the first through n-th impedance elements and allowing the selected one of the overall impedances to appear across the pair of external terminals, the overall impedances having therebetween a substantially constant step difference.
The present invention also provides, in a second aspect thereof, a variable impedance circuit including: a pair of external terminals; an impedance block including first through n-th impedance elements; and a control section for switching each of the impedance elements for connection between the pair of external terminals, thereby selecting one of overall impedances of the first through n-th impedance elements and allowing the selected one of the overall impedances to appear across the pair of external terminals, the overall impedances having a step difference profile which follows a linear function of xe2x80x9cixe2x80x9d, given xe2x80x9cixe2x80x9d being a sequential number of each of the first through n-th transistors.
In accordance with the variable impedance circuits of the present invention, the specified step difference or the specified step difference profile allows the variable impedance circuit to have an accurate design impedance even in the case of characteristic variances of the impedance elements.
The above and other objects, features and advantages of the present invention will be more apparent from the following description, referring to the accompanying drawings.